All Time Hardware Design Interview Questions
1. Draw a Transmission Gate-based D-Latch?
The Transmission-Gate’s input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D_LATCH enable input (EN) and the Transmission-Gate output is the D_LATCH output (Q)
2. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal?
Use the concept of register-retiming.
divide the total combinatorial delay in two segments such that individually the delay is less the clock period.
this can be done by inserting a flip-flop in the combinational path.
e.g,
clock period — 5 ns
total cominational delay —- 7
then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flip-flop in between.
3. How do you detect a sequence of “1101” arriving serially from a signal line?
Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero.
Ex : if the given sequence to be detected is 111
and input stream is 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1
the output should be 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1.
Soln:
One of the different possible ways to detect a sequence is using a Mealy type FSM.
4. Give the truth table for a Half Adder. Give a gate level implementation of the same.
TRUTH TABLE FOR HALF ADDER:
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
IMPLEMENTATION:
For SUM, The two inputs A and B are given to XOR gate.
For Carry, The two inputs A and B are given to AND gate.
5. Design a divide-by-3 sequential circuit with 50% duty circle.
Take a smiths counter with 3 f/f’s
that is to say with 6 states(2*3)
now double the i/p clock frequency to the counter
the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle so effectively u got divide by 3 freq with 50% duty cycle
6. Give two ways of converting a two input NAND gate to an inverter.
One way is shorting the two inputs of the NAND gate and passing the input.
Truth table:
A B output
1 1 0
0 0 1
The second way is passing the input to only one input(say A) of the NAND gate.Since the other input(say B) is floating, it is always logic one.
truth table:
A B output
1 1 0
0 1 1
7. How do you detect if two 8-bit signals are same?
XOR each bits of A with B (for eg A[0] xor B[0] ) and
so on. the o/p of 8 xor gates are then given as i/p to
an 8-i/p nor gate. if o/p is 1 then A=B.
8. Give a circuit to divide frequency of clock cycle by two?
You can divide the frequency of a clock by just implementing T Flip flop.
Give clock as clock input and tie the T input to logic 1.
9. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Suppose your flip-flop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint .
Time for which data should be stable after the positive edge of clock is called as hold time constraint.
if any of these constraints are violated then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.
there are two equation:
1. Tcq + Tcomb> Tskew + Thold
2. Tcq + Tcomb